1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device, in which an inverted sidewall spacer LDD(Lightly Doped Drain) structure is employed for securing a fabrication allowance and improving a device packing density; and a method for fabricating the same.
2. Background of the Related Art
A related art semiconductor device and method for fabricating the same will be explained with reference to the attached drawings. The related art semiconductor device is provided with a device isolating layer 2 of STI structure stuffed in a trench of a depth in a device isolation region, a gate electrode 5 of a planar structure on an active region defined by the device isolating layer 2, gate sidewalls 7a at sides of the gate electrode 5, source/drain regions having LDD regions 6a and 6b in surfaces of the semiconductor substrate under the gate sidewalls 7a and highly doped impurity regions 8a and 8b in surfaces of the semiconductor substrate 1 on both sides of the gate sidewalls 7a and the gate electrode 5, an interlayer insulating layer 9 having contact holes to the source/drain regions selectively, and metal electrode layers 10a and 10b in contact with the source/drain regions through the contact holes in the interlayer insulating layer 9, respectively. The LDD regions 6a and 6b is formed between a channel region under the gate electrode 5 and the highly doped impurity regions 8a and 8b. 
A related art method for fabricating a semiconductor device will be explained. FIGS. 1Axcx9c1H illustrate sections showing the steps of a related art method for fabricating a semiconductor device.
Referring to FIG. 1A, the related art method for fabricating a semiconductor device starts with forming an oxide film 2 and a nitride layer 3 on a semiconductor substrate 1 in succession. Then, as shown in FIG. 1B, the nitride layer 3 and the oxide film 2 are removed selectively by photolithography, and exposed portions of the semiconductor substrate 1 are etched to a depth, to form trenches. The trenches are stuffed with an insulating material, and planarized, to form a device isolating layer 4 of an STI(Shallow Trench Isolation) structure. As shown in FIG. 1C, the nitride layer 3 is removed. And, as shown in FIG. 1D, a gate electrode 5 is formed on an active region defined by the device isolation layer 4. As shown in FIG. 1E, the gate electrode 5 is used as a mask in implanting impurities in the surfaces of the semiconductor substrate 1 lightly, to form LDD regions 6a and 6b. As shown in FIG. 1F, a gate sidewall forming material layer, such as an HLD(High Temperature Low Pressure Deposition) layer 7, is formed on an entire surface inclusive of the gate electrode 5. Then, as shown in FIG. 1G, the HLD layer 7 is etched back, leaving the HLD layer 7 on side surfaces of the gate electrode 5, to form gate sidewalls 7a. The gate electrode 5 inclusive of the gate sidewalls 7a is used as a mask in implanting impurities highly, to form source/drain regions having LDD regions 6a and 6b and impurity regions 8a and 8b. As shown in FIG. 1H, an interlayer insulating layer 9 is formed on an entire surface, and etched selectively, to expose the source/drain regions, to form metal electrode layers 10a and 10b. The related art method for fabricating a semiconductor device has a minimum line width in the gate electrode patterning fixed from a limitation of resolution of photolithography.
However, the related art semiconductor device and method for fabricating the same have the following problems.
The patterning of the gate electrode by photolithography and the planar gate electrode are difficult to apply to a method for fabricating a submicron device with a line width of the circuit in a range of 0.1 xcexcm. The limitation in reduction of line width of the circuit causes difficulty in securing a fabrication allowance in fabrication of devices of high device packing density. The wide variation of CD(Critical Dimension) in the gate electrode patterning causes difficulty in obtaining products with stable characteristics.
Accordingly, the present invention is directed to a semiconductor device and a method for fabricating the same that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a semiconductor device and a method for fabricating the same, which permits to secure a fabrication allowance and to improve a device packing density.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the semiconductor device includes a semiconductor substrate, a recessed channel region recessed below a surface of the semiconductor substrate, and a gate oxide film formed on the recessed channel region, a first and a second lightly doped impurity regions in surfaces of the substrate adjacent to, and on both sides of the recessed channel region respectively, and a first and a second highly doped impurity regions adjacent to the first and second lightly doped impurity regions, respectively, inverted sidewalls on the first and second lightly doped impurity regions each having a round in a side of the recessed channel region, and a gate electrode both on the inverted sidewalls and the recessed channel region.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor device, including the steps of (1) forming an oxide film and a nitride film on a semiconductor substrate in succession and patterning selectively, and forming trenches using the patterned oxide film and the nitride film, (2) stuffing an insulating material in the trenches, to form device isolating layers, (3) removing a width of the nitride film on an active region defined by the device isolating layers, to form a channel defining trench, (4) using the patterned nitride film as a mask in implanting impurities lightly, to form lightly doped impurity regions for forming LDDs, (5) forming inverted sidewalls at sides of the channel defining trench, and oxidizing a bottom portion, to form the LDD regions, (6) removing the oxide film on a bottom surface of the channel defining trench, to form a channel of semispherical recess with a depth, (7) removing the nitride layer, forming a gate oxide film on a surface of a recessed channel region, and forming a gate electrode both on the inverted sidewalls and the gate oxide film, and (8) using the gate electrode inclusive of the inverted sidewalls as a mask in implanting impurities, heavily.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.